`timescale 1ns / 10ps
module multi_bit_test;

	parameter WIDTH = 4;

	reg		[WIDTH-1:0] a_in, b_in;
	wire	[WIDTH-1:0] s_out;
	
	wire c_out;

	integer i;

	// sadly we have to pass actual number as parameter, no integer, neither
	// outer parameter.
	multi_bit_full_adder #(4) sbfa (.A(a_in), .B(b_in), .S(s_out), .cout(c_out));

	initial begin

		$dumpfile("mbfa.vcd");
		$dumpvars(0, multi_bit_test);
		
		{a_in, b_in} <= 0;

		for (i = 0; i < 2 ** (WIDTH * 2); i+=1) begin
			#10;
		 	$monitor("A=0x%0h B=0x%0h Sout=0x%h Cout=0x%h", a_in, b_in, s_out, c_out);
			{a_in, b_in} <= i;
		end
		#10 $monitor("DONE");

	end

endmodule
